Discrete Amplifiers — Bias and Gain

Overview

Focuses on single‑stage amplifier topologies (common‑emitter, common‑source), biasing methods for stability, coupling capacitors, and interaction with load and source impedances.

Prerequisites

• Understanding of transistor small‑signal parameters (see previous chapter)

Learning objectives

• Design bias networks that stabilise operating points over temperature and device variation
• Compute voltage gain, input and output impedance for common topologies
• Choose coupling and bypass capacitors to achieve desired low‑frequency response

Hands-On Mini Task

1. Design and build a common‑source MOSFET amplifier, set a quiescent current, and measure gain and input/output impedance.
2. Add an emitter/source degeneration resistor and observe the effect on gain linearity and input impedance.

Expected result: improved linearity with degeneration and predictable changes in gain matching hand calculations.

Theory

Common topologies: common-emitter/source (voltage gain), common-collector/drain (emitter/source follower for buffering). Gain is set by load and intrinsic device parameters; emitter/source degeneration linearises and raises input impedance.

Practical design notes

• Choose bias current to balance noise, linearity, and power.
• Consider coupling caps to block DC between stages; calculate high-pass cutoff fc = 1/(2πRC).

Worked example — setting bias for a MOSFET stage

1. Select target quiescent current (e.g., 1 mA). Choose R_D and R_S to set V_DS and V_GS for the chosen Id using device curves or SPICE.
2. Verify small-signal gain with hand calculation and simulation.

Troubleshooting

• If DC offset is large at the output, check coupling capacitors and bias network values.
• Oscillation at high gain: check layout, add small compensation or series resistors at inputs.

Navigation

• Previous: Semiconductor Devices — BJTs and MOSFETs
• Next: Active Filters Workshop